Job Details
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| ASIC Verification Engineer | | |
| Location | | Eastern ( Cambridgeshire ) | | |
Salary
Negotiable | | |
Benefits
£NEG + Excellent benefits package | | |
Application Deadline
13/08/2008 | | |
Description
ASIC VERIFICATION ENGINEER / CAMBRIDGESHIRE
£NEG + EXCELLENT BENEFITS PACKAGE
* Experienced ASIC Verification Engineer required to verify innovative network display ASICs, in particular working on PCI Express. This challenging role focuses on defining & implementing SoC & module level functional verification environments using latest advanced verification techniques; also making use of high level verification languages & associated methodologies
* May also involve many, or all, parts of development flow from block or system level specification & RTL design of modules for use in ASIC or FPGA, through functional verification, synthesis & timing closure, to silicon validation & production test
We are keen to hear from experienced ASIC VERIFICATION ENGINEERS with experience as follows:
- High-level Verification Language (e.g SystemVerilog preferred, Vera, ?e' or SystemC)
- Developing verification plans from scratch
- Architecting layered, re-usable, self-checking testbenches
- Methodology: e.g AVM preferred, RVM, VMM, eRM or OSCI TLM
- Verification techniques: Constrained Random Testing, Functional Coverage, Assertion Based Verification & Coverage, Scoreboards, Protocol Monitors
- SoC designs
- RTL design (VHDL / Verilog) | | |
Reference
41937 | | |
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This job has now expired.
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